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MC14512B 8-Channel Data Selector
The MC14512B is an 8-channel data selector constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. This data selector finds primary application in signal multiplexing functions. It may also be used for data routing, digital signal switching, signal gating, and number sequence generation.
Features
http://onsemi.com MARKING DIAGRAMS
16 MC14512BCP AWLYYWWG 1
* * * * * *
Diode Protection on All Inputs Single Supply Operation 3-State Output (Logic "1", Logic "0", High Impedance) Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range Pb-Free Packages are Available*
PDIP-16 P SUFFIX CASE 648 1
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, Per Package (Note 1) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Value -0.5 to +18.0 -0.5 to VDD + 0.5 10 500 -55 to +125 -65 to +150 260 Unit V V mA mW C C C A WL YY, Y WW G 1
SOIC-16 D SUFFIX CASE 751B
16 14512BG AWLYWW 1
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
November, 2006 - Rev. 7
Publication Order Number: MC14512B/D
MC14512B
TRUTH TABLE
C 0 0 0 0 1 1 1 1 X X NOTE: B 0 0 1 1 0 0 1 1 X X X = Don't Care A 0 1 0 1 0 1 0 1 X X Inhibit 0 0 0 0 0 0 0 0 1 X Disable 0 0 0 0 0 0 0 0 0 1 Z X0 X1 X2 X3 X4 X5 X6 X7 0 High Impedance
PIN ASSIGNMENT
X0 X1 X2 X3 X4 X5 X6 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD DIS Z C B A INH X7
ORDERING INFORMATION
Device MC14512BCP MC14512BCPG MC14512BD MC14512BDG MC14512BDR2 MC14512BDR2G Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) 2500 / Tape & Reel 48 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC14512B
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 "1" Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Input Current Input Capacitance (Vin = 0) Quiescent Current (Per Package) Total Supply Current (Note 3) (Note 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) 3-State Leakage Current Source VIH 5.0 10 15 IOH 5.0 5.0 10 15 IOL 5.0 10 15 15 - 5.0 10 15 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 0.64 1.6 4.2 - - - - - - - - - - - - 0.1 - 5.0 10 20 - 2.4 - 0.51 - 1.3 - 3.4 0.51 1.3 3.4 - - - - - - 4.2 - 0.88 - 2.25 - 8.8 0.88 2.25 8.8 0.00001 5.0 0.005 0.010 0.015 - - - - - - - 0.1 7.5 5.0 10 20 - 1.7 - 0.36 - 0.9 - 2.4 0.36 0.9 2.4 - - - - - - - - - - - - 1.0 - 150 300 600 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - mAd c - 55_C 25_C 125_C Characteristic Symbol VOL Min - - - 4.95 9.95 14.95 - - - Max Min - - - 4.95 9.95 14.95 - - - Typ (Note 2) 0 0 0 5.0 10 15 2.25 4.50 6.75 Max Min - - - 4.95 9.95 14.95 - - - Max Unit Vdc Output Voltage Vin = VDD or 0 "0" Level 0.05 0.05 0.05 - - - 1.5 3.0 4.0 0.05 0.05 0.05 - - - 1.5 3.0 4.0 0.05 0.05 0.05 - - - 1.5 3.0 4.0 Vdc "1" Level Vin = 0 or VDD Input Voltage (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) "0" Level VOH Vdc VIL Vdc Sink mAd c mAdc pF mAdc Iin Cin IDD IT IT = (0.8 mA/kHz) f + IDD IT = (1.6 mA/kHz) f + IDD IT = (2.4 mA/kHz) f + IDD mAdc ITL 15 - 0.1 - 0.0001 0.1 - 3.0 mAdc 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001.
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C, See Figure 1)
All Types Characteristic Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns Propagation Delay Time (Figure 2) Inhibit, Control, or Data to Z Symbol tTLH, tTHL VDD 5.0 10 15 5.0 10 15 tPHL 5.0 10 15 tPHZ, tPLZ, tPZH, tPZL 5.0 10 15 330 125 85 60 35 30 650 250 170 150 100 75 ns Typ (Note 6) 100 50 40 330 125 85 Max 200 100 80 ns 650 250 170 ns Unit ns
tPLH
Propagation Delay Time (Figure 2) Inhibit, Control, or Data to Z
3-State Output Delay Times (Figure 3) "1" or "0" to High Z, and High Z to "1" or "0"
5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance.
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MC14512B
ID DISABLE INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7 VSS Z CL VDD
Vin
50% 50% DUTY CYCLE
PULSE GENERATOR
Figure 1. Power Dissipation Test Circuit and Waveform
VDD
20 ns DATA 90% 50% 10% 90% 50% 10% tTLH
20 ns VDD tPHL VSS VOH VOL
PULSE GENERATOR
DISABLE INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7 VSS
Z CL Z
tPLH
TEST CONDITIONS: INHIBIT = VSS A, B, C = VSS 20 ns 90% 50% 10% 90% 50% 10%
tTHL
20 ns INHIBIT, A, B, OR C Parameter Inhibit to Z A, B, C to Z Test Conditions A, B, C = VSS, XO = VDD Inh = VSS, XO = VDD Z tTHL tPHL
VDD VSS VOH VOL
tPLH
tTLH
Figure 2. AC Test Circuit and Waveforms
VDD PULSE GENERATOR VDD S3 S4 DISABLE INHIBIT A B C X0 X1 X2 X3 X4 X5 X6 X7 VSS VDD Z CL 1k S1 S2 VSS 20 ns DISABLE INPUT tPLZ OUTPUT tPHZ OUTPUT 90% 10% 90% 50% 10% 20 ns VSS tPZL VOH 90% VOL tPZH 10% VOH VOL VDD
VSS
2.5 V @ VDD = 5 V, 10 V, AND 15 V 2 V @ VDD = 5 V 6 V @ VDD = 10 V 10 V @ VDD = 15 V
Switch Positions for 3-State Test
Test tPHZ tPLZ tPZL tPZH S1 Open Closed Closed Open S2 Closed Open Open Closed S3 Closed Open Open Closed S4 Open Closed Closed Open
Figure 3. 3-State AC Test Circuit and Waveform http://onsemi.com
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MC14512B
13 12 11 1 2 3 4 5 6 7 9 IN VSS ITL MC14512B 14 Z MC14512B ITL
LOGIC DIAGRAM
C B A X0 X1 X2 X3 X4 X5 X6 X7
15 DISABLE 10 INHIBIT VDD SELECTED DEVICE MC14512B DATA BUS IOD IL
LOAD
1 OUT IN
1 OUT 2
2 TRANSMISSION GATE
3-STATE MODE OF OPERATION Output terminals of several MC14512B 8-Bit Data Selectors can be connected to a single date bus as shown. One MC14512B is selected by the 3-state control, and the remaining devices are disabled into a high-impedance "off" state. The number of 8-bit data selectors, N, that may be connected to a bus line is determined from the output drive current, IOD, 3-state or disable output leakage current, ITL, and the load current, IL, required to drive the bus line (including fanout to other device inputs), and can be calculated by:
N= IOD - IL +1 ITL
N must be calculated for both high and low logic state of the bus line.
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MC14512B
PACKAGE DIMENSIONS
PDIP-16 CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16 CASE 751B-05 ISSUE J
-A-
16 9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
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MC14512B
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC14512B/D

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